1. Field of the Invention
The present invention relates to a reprogrammable built-in-self-test integrated circuit and a test method for the same, particularly to a reprogrammable built-in-self-test Multi-Chip-Package System-on-Chip Integrated Circuit (MCP SoC IC) and a method for the same.
2. Description of the Related Art
In an MCP SoC IC, a plurality of chips is packaged together, including a logic chip and a memory chip, which are electrically connected by bonding wires. In other words, a system chip and a memory chip (such as a flash memory, a SRAM (Static Random Access Memory), or a SDRAM (Synchronous Dynamic Random Access Memory)) are usually integrated into an MCP SoC IC. However, the IC package process usually causes open circuit or short circuit of bonding wires.
After package, a final test is often performed to check the bonding-wire connectivity. Below, the existing final tests for bonding-wire connectivity are described.
Firstly, a dedicated BIST circuit is sometimes embedded inside IC to test a memory. The dedicated BIST circuit can automatically generate pre-defined test vectors to execute memory-read and memory-write activities and compares the execution results and then outputs the test result via pins. In such an approach, special test vectors should be designed beforehand according to the arrangement of bonding pads. Once there is any slight change in the arrangement of bonding pads during the layout process, the embedded BIST circuit should be redesigned also. However, the arrangement of bonding pads will not settle until the last stage. Therefore, although test coverage is found to be insufficient, test vectors cannot be changed any more in this approach after the completion of a chip. Besides, the dedicated BIST circuit of this approach cannot apply to memory chips with different memory densities because of its inflexibility. In addition, test failures cannot be further analyzed after a completed chip is tested in this approach.
There is also a test method of directly writing/reading a memory, wherein the address bus, the data bus, and other control signals of a memory are connected to pins on the surface of IC, and a test apparatus generates test signals to perform an access test on the memory inside IC. In this approach, a small-package IC may have insufficient pins to connect with control signals or even need additional multiplexing circuits to switch pins, which will make the I/O design more complicated. Besides, this approach can only test the connectivity between a memory and pins but cannot test the connectivity between the memory and a CPU core.
There is also a test method of using an embedded CPU, wherein a test program is beforehand burned on a special storage space, such as a ROM. The test program is separated from the main program; during a test, the program source is switched to the dedicated storage space for the test program. Alternatively, the test program is incorporated with the main program to form a single program; during a test, the main program is switched to a test mode, and the test is undertaken under the test mode. During the test, the memory-read and memory-write activities are performed, and the test data is compared and analyzed, and then the final result is output. A US pub patent No: US20030023914 A1 exactly adopts this approach. In the test method of using an embedded CPU, the test program is incorporated with the main program or occupies some memory space. However, the IC does not use the test program in normal operations. Thus, the hardware resource of IC is wasted. Besides, the test program is settled before tapeout. After the chip is completed, the test program is unlikely to be revised. Therefore, neither test coverage improvement nor failure analysis & diagnosis is available in this approach.
Accordingly, the present invention proposes a reprogrammable built-in-self-test integrated circuit and a test method for the same to overcome the abovementioned problems.